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| CY2XL11 100 MHz LVDS Clock Generator Features Functional Description The CY2XL11 is a PLL (Phase Locked Loop) based high performance clock generator with a crystal oscillator interface and one LVDS output pair. It is optimized to generate PCI Express, FC, and other high performance clock frequencies. It also produces an output frequency that is four times the crystal frequency. It uses Cypress's low noise VCO technology to achieve less than 1 ps typical RMS phase jitter, that meets high performance systems' jitter requirements. One LVDS Output Pair Output Frequency: 100 MHz External Crystal Frequency: 25 MHz Low RMS Phase Jitter at 100 MHz, using 25 MHz Crystal (637 kHz to 10 MHz): 0.53 ps (Typical) Pb-free 8-Pin TSSOP Package Supply Voltage: 3.3V or 2.5V Commercial Temperature Range Logic Block Diagram XIN External Crystal XOUT OE CRYSTAL OSCILLATOR LOW-NOISE PLL OUTPUT DIVIDER CLK CLK# Pinouts Figure 1. Pin Diagram - 8-Pin TSSOP VDD VSS XOUT XIN Table 1. Pin Definition - 8-Pin TSSOP Pin Number 1, 8 2 3, 4 5 6,7 Pin Name VDD VSS XOUT, XIN OE CLK#, CLK I/O Type Power Power 1 2 3 4 8 7 6 5 VDD CLK CLK# OE Description 3.3V or 2.5V power supply. All supply current flows through pin 1 Ground Parallel resonant crystal interface Output Enable. When HIGH, the output is enabled. When LOW, the output is high impedance Differential clock output XTAL output and input CMOS input LVDS output Cypress Semiconductor Corporation Document Number: 001-42886 Rev. *C * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised June 12, 2009 [+] Feedback CY2XL11 Frequency Table Input Crystal Frequency (MHz) 25 PLL Multiplier Value 4 Output Frequency (MHz) 100 Absolute Maximum Conditions Parameter VDD VIN[1] TS TJ ESDHBM UL-94 JA[2] Description Supply Voltage Input Voltage, DC Temperature, Storage Temperature, Junction ESD Protection (Human Body Model) Flammability Rating Thermal Resistance, Junction to Ambient JEDEC STD 22-A114-B At 1/8 in. 0 m/s airflow 1 m/s airflow 2.5 m/s airflow 2000 V-0 100 91 87 C/W Relative to VSS Non operating Condition Min -0.5 -0.5 -65 Max 4.4 VDD + 0.5 150 135 Unit V V C C V Operating Conditions Parameter VDD TA TPU 3.3V Supply Voltage 2.5V Supply Voltage Ambient Temperature Power up time for all VDD to reach minimum specified voltage (ensure power ramps is monotonic) Description Min 3.135 2.375 -5 0.05 Max 3.465 2.625 70 500 Unit V V C ms DC Electrical Characteristics Parameter IDD[4] Description Test Conditions Min - - 250 - 1.125 - -35 Typ - - - - - - - Max 120 115 450 50 1.375 50 35 Unit mA mA mV mV V mV A Power Supply Current with output VDD = 3.465V, OE = VDD, output termiterminated nated VDD = 2.625V, OE = VDD, output terminated VOD[6] VOD[6] VOS[7] VOS IOZ LVDS Differential Output Voltage VDD = 3.3V or 2.5V, RTERM = 100 between CLK and CLK# Change in VOD between Comple- VDD = 3.3V or 2.5V, RTERM = 100 mentary Output States between CLK and CLK# LVDS Offset Output Voltage VDD = 3.3V or 2.5V, RTERM = 100 between CLK and CLK# Change in VOS between Comple- VDD = 3.3V or 2.5V, RTERM = 100 mentary Output States between CLK and CLK# Output Leakage Current Three-state output, PD#/OE = VSS Notes 1. The voltage on any input or IO pin cannot exceed the power pin during power up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. Outputs are terminated with 100 between CLK and CLK#. Refer to Figure 8 on page 5. 4. IDD includes ~4 mA of current that is dissipated externally in the output termination resistor. 5. Not 100% tested, guaranteed by design and characterization. 6. Refer to Figure 2 on page 4. 7. Refer to Figure 3 on page 4. Document Number: 001-42886 Rev. *C Page 2 of 7 [+] Feedback CY2XL11 DC Electrical Characteristics (continued) Parameter VIH VIL IIH IIL CIN CINX Description Input High Voltage, OE pin Input Low Voltage, OE pin Input High Current, OE pin Input Low Current, OE pin Input Capacitance, OE pin Pin Capacitance, XIN & XOUT OE = VDD OE = VSS Test Conditions Min 0.7*VDD - - -50 Typ - - - - 15 4.5 Max - 0.3*VDD 115 - Unit V V A A pF pF AC Electrical Characteristics[3] Parameter FOUT TR, TF[8] TJitter()[11] TDC[9] TOHZ[10] TOE[10] TLOCK Description Output Frequency Output Rise or Fall time RMS Phase Jitter (Random) Duty Cycle Output Disable Time Output Enable Time 20% to 80% of full output swing FUT =100 MHz, (637 kHz-10 MHz) Measured at zero crossing point Time from falling edge on OE to stopped outputs (Asynchronous) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) Min - - - 45 - - Typ 100 500 0.53 - - - Max - - - 55 100 100 Unit MHz ps ps % ns ns Startup Time - - 10 ms Crystal Characteristics Parameter Mode of Oscillation F ESR CS Frequency Equivalent Series Resistance Shunt Capacitance Description Min 25 - - Max 25 50 7 Unit MHz pF Fundamental Notes 8. Refer to Figure 4 on page 4. 9. Refer to Figure 5 on page 4. 10. Refer to Figure 6 on page 4. 11. Refer to Figure 7 on page 5. Document Number: 001-42886 Rev. *C Page 3 of 7 [+] Feedback CY2XL11 Switching Waveforms Figure 2. Output Voltage Swing CLK# VOD1 CLK VOD = VOD1 - VOD2 Figure 3. Output Offset Voltage VOD2 CLK 50 50 CLK# V OS Figure 4. Output Rise or Fall Time CLK# 20% TR 80% 80% 20% TF CLK Figure 5. Duty Cycle Timing CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Figure 6. Output Enable and Disable Timing OE VIL VIH TOHZ CLK TOE High Impedance CLK# Document Number: 001-42886 Rev. *C Page 4 of 7 [+] Feedback CY2XL11 Figure 7. RMS Phase Jitter Phase noise Noise Power Phase noise mark Offset Frequency f1 RMS Jitter = f2 Area Under the Masked Phase Noise Plot Termination Circuits Figure 8. LVDS Termination CLK 100 CLK# Document Number: 001-42886 Rev. *C Page 5 of 7 [+] Feedback CY2XL11 Ordering Information Part Number CY2XL11ZXC CY2XL11ZXCT 8-pin TSSOP 8-pin TSSOP - Tape and Reel Package Description Product Flow Commercial, -5C to 70C Commercial, -5C to 70C Package Drawing and Dimensions Figure 9. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 8 0.19[0.007] 0.30[0.012] 0.65[0.025] BSC. 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0-8 0.076[0.003] 0.85[0.033] 0.95[0.037] 2.90[0.114] 3.10[0.122] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85093-*A Document Number: 001-42886 Rev. *C Page 6 of 7 [+] Feedback CY2XL11 Document History Page Document Title: CY2XL11 100 MHz LVDS Clock Generator Document Number: 001- 42886 REV. ** *A ECN NO. 2117527 2669117 Submission Date See ECN 03/05/2009 Orig. of Change WWZ/KVM New data sheet /AESA KVM/ AESA Changed crystal and output frequency Removed MSL spec Changed IIL value from -20 uA to -50 uA Changed IIH value from 20 uA to 115 uA Changed phase jitter value from 1 to 0.53 ps Changed junction temp from 125C to 135C Changed IDD from 150 mA to 120 mA Rise / fall time changed to 350 ps to 500ps Changed Data Sheet Status to Final Typo correction Reformatted AC and DC tables Added IDD spec for 2.5V Added CINX and TLOCK specs Changed CIN from 7pF to 15pF Description of Change *B 2700242 04/30/2009 KVM/ PYRS *C 2718433 06/12/2009 WWZ/HMT No change. Submit to ECN for product launch. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-42886 Rev. *C Revised June 12, 2009 Page 7 of 7 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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